A charged particle beam apparatus is one which is able to produce a 2-dimensional image of a wafer substrate by detecting secondary electrons, backscattered electrons, mirror electrons, or other kind of electrons from the surface of the wafer substrate upon impingement by a charged particle beam generated by a charged particle beam apparatus. Various charged particle beam apparatus are used on semiconductor wafers in the semiconductor industry for various purposes such as wafer processing (for example, e-beam direct-write lithography system), process monitoring (for example, critical dimension scanning electron microscope, or CD-SEM), wafer inspection (for example, e-beam inspection system), defect analysis (for example, defect review SEM, or DR-SEM and Focused Ion Beam system, or FIB), etc. When such an apparatus performs its function, the electrical potential of the wafer substrate needs to be held at a predetermined value, i.e. the wafer substrate has to be biased. This can be achieved by electrically, or more specifically, resistively connecting the target wafer substrate to a programmable DC (direct current) voltage source (i.e. Wafer Bias Supply) when the wafer substrate interacts with the charged particle beam, during which process excess charges are brought to the wafer substrate. This process will be referred to as “wafer biasing” in this specification.
For wafer biasing, the electrical contact from the wafer bias supply to the wafer substrate is conventionally made at the backside of the wafer substrate by using electrical contact(s) which press against the backside surface of the wafer substrate as the front surface of the wafer is inappropriate to place the electrical contact. However, the backside surface of the wafer substrate is usually covered by thin layers of dielectric materials such as silicon oxide and nitrides, created as sub-products of wafer manufacturing process steps. Therefore, the required conductance between the contact(s) and the wafer substrate generally cannot be established by simply pressing the contact(s) against the wafer's backside surface. A stable and low-resistance DC path(s) between the electrical contact(s) and the wafer substrate must be established first. Such action is often referred to as “wafer grounding”, and the term will be used throughout this application while the electrical contacts are called “pulse current pins” or “neutralizing pins”.
One of the conventionally used methods for wafer grounding is the mechanical piercing method. In this method, the pulse current pin is made of a hard conductive material with a very sharp tip, which is used to physically pierce through the backside films and makes direct contact to the wafer substrate thereby establishing a stable and low-resistance DC path, which will be referred to as a wafer bias current path hereinafter, between the pulse current pin and the substrate as the pulse current pin is pressed against the backside surface of the wafer. The mechanical piercing method is simple and reliable, but it tends to create a large number of particles which may interfere with efforts to obtain high manufacturing yield of the finished products, i.e. semiconductor chips.
Another method commonly used is the electrical zapping method. FIG. 1 schematically illustrates the concept of a conventional wafer grounding/wafer biasing apparatus employing the electrical zapping method. A wafer backside film (s) 12 is present on the back of a wafer substrate 13. Two contact pins 11A and 11B pressing against the wafer backside film(s) 12 are used as the pulse current pin and neutralizing pin, and a high voltage pulse or pulses are applied between the pulse current pin 11A and neutralizing pin 11B by a grounding pulse generator 14 via a resistor 101R. Unlike the mechanical piercing method, the electrical zapping method does not pierce through the backside film. The process produces two current paths, one 15A between the drive-side pulse current pin 11A and the wafer substrate 13 and the other 15B between the return-side neutralizing pin 11B and the wafer substrate 13.
A drive-side pulse current pin is a pin for creating a current path through which a current flows into the wafer substrate 13, and a return-side neutralizing pin is for creating another current path through which a current flows out of the water substrate 13. The electrical zapping method involves two successive dielectric breakdowns, the first between the pulse current pin 11A and the wafer substrate 13 whereupon the current path 15A is created, and the second between the neutralizing pin 11B and the wafer substrate 13 whereupon the current path 15B is established. When pulsing (by grounding pulse generator 14) is done and both of the current paths 15A/15B yield a stable and low-resistance DC path, two wafer bias current paths are established, with one between pulse current pin 11A and the wafer substrate 13 (will still be referred to as 15A) and the other between the neutralizing pin 11B and the wafer substrate 13 (will still be referred to as 15B). The wafer grounding is thus completed.
After the wafer grounding is completed, the pulse current pin 11A and neutralizing pin 11B are electrically disconnected from the grounding pulse generator 14 and the connection to the system ground, respectively, and the current return path from the wafer substrate 13 to the system ground is now switched to be connected to a wafer bias supply 16. The wafer bias supply 16 is for providing the proper bias voltage to the wafer substrate 13 through the above established two wafer bias current paths 15A/15B.
For more accurate description of the wafer grounding process, the following stray capacitances are taken in considerations. Small stray capacitances C1 and C2 are parasitic to the pulse current pin 11A and neutralizing pin 11B, respectively. The pulse current pin 11A and neutralizing pin 11B are coupled to the system ground or the equivalent through the capacitances C1 and C2, respectively. Capacitance C3 is parasitic to wafer substrate 13. The wafer substrate 13 is coupled to the system ground or the equivalent through capacitance C3.
When the wafer grounding is being performed, the puke current pin 11A should be connected with the grounding pulse generator 14 i.e. node 102A is connected with node 102D, and the neutralizing pin 11B should be electrically connected to the system ground i.e. node 102B is connected with node 102G.
As an initial state, the tips of the pulse current pin 11A and neutralizing pin 11B are pressed against the surface of the backside films 12. The wafer substrate 13 is electrically floated. DC wise, being isolated from the pulse current pin 11A and neutralizing pin 11B by the backside dielectric film(s) 12. The potential of the substrate 13 is electro-statically held near ground level by capacitance C3.
A high-voltage (e.g., greater than 100 volts) grounding pulse or pulses are then applied from the grounding pulse generator 14 to the pulse current pin 11A, via a resistor 101R and a connected switch SW (node 102A connected with node 102D, and node 102B connected with node 102G). When being applied to the pulse current pin 11A, the grounding pulse(s) also charge up stray capacitance C1 and a small capacitance formed between the pulse current pin 11A and the wafer substrate 13.
Very high electrical field is formed across the backside dielectric films 12 between pulse current pin 11A and wafer substrate 13 (whose potential is held near ground level by the capacitance C3). This high electrical field causes a dielectric breakdown, the first dielectric breakdown, through the backside films 12 between the pulse current pin 11A and the wafer substrate 13. A breakdown current thus flows through the backside films 12. The breakdown current is a very intense, short-duration pulse current sourced by the stray capacitance C1 and the small capacitance between the pulse current pin 11A and the substrate 13. The flow of the breakdown current yields an initial current path 15A between the pulse current pin 11A and the wafer substrate 13. The current path 15A initially may not necessarily be a stable current path and may be only temporarily present. Immediately following the breakdown current, additional current sourced by the grounding pulse generator 14 via resistor 101R starts to flow through the initial current path 15A. This subsequent current is named “grounding pulse current” for convenience of description in this application. There is no clear separation between the breakdown current and the grounding pulse current. However, the grounding pulse current may continue to flow until the grounding pulse generator 14 ceases pulsing. The grounding pulse current may reduce and/or stabilize the resistance of the current path 15A.
Generally, the dielectric breakdown process induces a structural damage on the backside dielectric films in the vicinity of the pulse current pin, with a magnitude depending on the energy involved. The grounding pulse current may also lead to further damages on the backside film(s) 12 as it continues.
The current flowing into wafer substrate 13 (the breakdown current and the grounding pulse current combined) charges the capacitance C3, raising the electrical potential of the wafer substrate 13. Accordingly, a very high electrical field across the backside dielectric films 12 is formed between the wafer substrate 13 and the neutralizing pin 11B and causes another dielectric breakdown, the second dielectric breakdown, through the backside films 12 between the wafer substrate 13 and the neutralizing pin 11B, initiating a current path 15B. This time, the breakdown current (mainly sourced by the stray capacitance C2 and the small capacitance between the neutralizing pin 11B and the wafer substrate 13) may further include a rush current sourced by the charge stored in the capacitance C3 as the neutralizing pin 11B is connected to the ground through the low resistance DC path. As the current path 15B is generated, it will provide a DC return path for the grounding pulse current, increasing the current flowing through the current path 11A from the resistor 101R and letting a good portion of the current flow down to ground through the current path 15B and the rest flow into capacitance C3.
The breakdown current at the second break down produces a structural damage on the backside film(s) 12 in the vicinity of the neutralizing pin 11B. As the grounding puke current continues flowing until the grounding pulse(s) ceases, further structural damages may be caused on the backside films 12 in the vicinities of the pulse current pin 11A and neutralizing pin 11B. At the same time the resistances of the current paths 15A/15B may be reduced and/or stabilized.
When the grounding pulse generator 14 completes the last grounding pulse and each of the current paths 15A/15B yields a stable and low-resistance DC path, a wafer bias current path is established at the same position of the individual current path 15A/5B, and the wafer grounding process is completed. The established wafer bias current paths will still be referred to as 15A (between pulse current pin 11A and substrate 13) and 15B (between neutralizing pin 11B and substrate 13), respectively.
The overall wafer grounding/biasing process is then to be taken into the next phase, the wafer biasing process. The pulse current pin 11A and neutralizing pin 11B are electrically disconnected from the grounding pulse generator 14 and the connection to the system ground, respectively. Then, the both of the pulse current pin 11A and neutralizing pin 11B are now connected to the wafer bias supply 16, i.e. node 102A is connected with node 102C and node 102B is connected with node 102F, in order to provide the proper bias voltage to the wafer substrate 13 through the wafer bias current paths for the subsequent operation.
Referring to FIG. 2, which is a schematic illustration of in-practice instrumentation of the conventional wafer grounding/wafer biasing apparatus. As shown, a wafer mount 17, such as an electrostatic chuck (e-chuck), is used to hold or support the wafer substrate 13. Before the wafer grounding is performed, the wafer substrate 13 needs be clamped by the e-chuck 17, which usually includes at least one positive electrode 17A (driven by a positive DC voltage V+), and at least one negative electrode 17B (driven by a negative DC voltage V−). An e-chuck power supply 19 supplies proper voltages to the positive electrode 17A and the negative electrode 17B.
Due to the substantially large areas of electrodes 17A/17B which face the wafer substrate 13 with a small distance, large capacitances between each electrode(s) 17A/17B and wafer substrate 13 are incurred. For example, there is a first chuck-referred capacitance Cw-ch+ between the wafer substrate 13 and the positive electrode(s) 17A, and a second chuck-referred capacitance Cw-ch− between the wafer substrate 13 and the negative electrode(s) 17B.
In FIG. 1, the substrate stray capacitance C3 is assumed to be small as FIG. 1 is a conceptual model of wafer grounding apparatus where the effect of the presence of e-chuck electrodes 17A, and 17B is not considered. However, in practice, such as in the configuration in FIG. 2, the size of the capacitance on the wafer substrate 13, Cw-ch+ and Cw-ch− combined, is substantially larger than the assumed capacitance C3 in FIG. 1. This may affect the structural damage actually caused to the backside film(s) 12 during the wafer grounding process.
For example, after the initial current path 15A is generated between the pulse current pin 11A and the wafer substrate 13 by the first dielectric breakdown, the incoming grounding pulse current needs to raise the potential of the wafer substrate 13 high enough to trigger the second dielectric breakdown between the wafer substrate 13 and the neutralizing pin 11B. This is done by the grounding pulse current charging the capacitances Cw-ch+ and Cw−Ch−, both of which are significantly larger than the assumed stray capacitance C3 in FIG. 1. As a result, more significant structural damage may be caused to the backside films 12 in the vicinity of the pulse current pin 11A as a much larger “net” current, i.e. the current integrated over time, flows through the current path 15A between the pulse current pin 11A and the substrate 13.
On the other hand, the rush current sourced by the capacitances Cw-ch+ and Cw-ch− running through the current path 15B created by the second dielectric breakdown between the wafer substrate 13 and the neutralizing pin 11B will take a longer time to decay as a large quantity of charge has been stored in the capacitances Cw-ch+ and Cw-ch− and needs to be released. Therefore, more severe structural damage on the backside film(s) in the vicinity of the neutralizing pin 11B may result.
For the foregoing discussions, a need has arisen to propose a novel wafer grounding/potential holding apparatus for solving the grounding damage problem.